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Board and enclosure FlatLock v0

A test board with an ESP32-C3 module and a 3D-printable enclosure. Schematic, board, checks and enclosure are all generated by scripts. The enclosure's dimensions are not read off a drawing but from the board's 3D model, so it fits the connector and the LED.

board 20.5 x 33.1 mm enclosure 25.3 x 37.9 x 16.2 mm DRC 0 errors KiCad + OpenSCAD

3D model: the board in its enclosure

The board is exported from KiCad with its components, copper and silkscreen; the enclosure and lid are the exact parts that go to the printer. The slider pulls the parts apart.

This is a test board from the FlatLock project, not the board the lock runs on today. It has not been manufactured or printed yet; what is verified and what is not is listed below.

The enclosure step by step

The board has no mounting holes, to keep it as small as possible. So the enclosure holds it differently: the board rests on a ledge around the edge and posts on the lid press it down from above. Every dimension is derived from the board.

Krok 1: deska se součástkami jako obalové kvádry

1Board from KiCad

Outline and component bodies from the board's 3D model. The ESP32-C3 module came out 2.39 mm tall; the datasheet says 2.4.

Krok 2: dno krabičky

2Base

1.6 mm with rounded corners. 0.4 mm clearance around the board on every side.

Krok 3: stěny krabičky

3Walls

Height is set by the tallest part: the J1 header stands 8.5 mm above the board, plus 0.5 mm margin.

Krok 4: lišta po obvodu, na které deska leží

4Ledge under the edge

J1 pins stick out 1.4 mm below the board, so the ledge holds it 2.4 mm above the base. A check makes sure it runs under no pin.

Krok 5: víko s lemem

5Lid with a lip

A 3 mm lip drops into the box with 0.2 mm clearance, to be tuned on the first print.

Krok 6: přítlačné sloupky a žebro na víku

6Posts and rib

Posts only in corners with nothing in the way: two of four qualified. A rib along the right edge, where 1.25 mm is left between the module and the edge.

Krok 7: průchod pro kabel nad konektorem a okénko nad LED

7Cable and LED

An opening right above J1 with 0.6 mm clearance for the cable connector, a 2.6 mm window above LED D1. Positions taken from the board.

Krok 8: větrací štěrbiny v bočních stěnách

8Vents

Three slots in each long wall next to the regulator, which dissipates 0.58 W at peak.

Oba díly na podložce tiskárny: krabička dnem dolů a víko obrácené vedle ní
Both parts print without supports: the box base-down, the lid upside down next to it. Outer size 25.3 x 37.9 x 16.2 mm.

Where the enclosure gets its dimensions

On the previous board, component positions were copied into the enclosure model by hand and ended up 10 mm off. Here no number is copied. When the board changes, the enclosure is recomputed with one command.

  1. Board in KiCad

    Placed according to the schematic's netlist.

  2. Board 3D model

    kicad-cli exports it including the package models.

  3. Component bodies

    A script reads the board outline and a box around each component.

  4. Enclosure model

    OpenSCAD derives the dimensions and stops on anything that would collide.

  5. STL and this page

    Print-ready parts, the step images and the 3D model above.

Why from the 3D model and not the board drawing: the package outline in the drawing is an assembly courtyard with an allowance, not the real body, and it has no height at all. The opening in the lid and the gap above the board need the actual body.

Schematic

Drawn as a document, not as a list of connections: power and functional blocks are drawn as wires; labels remain only where a wire would have to go around the whole module. After writing it, the script has KiCad export the netlist and compares it with the expected nets.

Schéma FlatLock v0: napájení 5 V přes AMS1117-3.3, modul ESP32-C3-MINI-1, RC článek na EN, LED na GPIO10 a programovací konektor J1
Click to open full size. ERC: 0 errors.

Connector J1

PinSignal
15 V
2GND
3TXD (module output)
4RXD (module input)
5EN (reset)
6IO9 (boot)

One cable both powers and programs the board. The LED is on GPIO10 because GPIO2, 8 and 9 decide the boot mode at startup and an LED to ground could pull them low.

The board

Two layers, 20.5 x 33.1 mm. The size follows the content, not a guess: the width is set by a corridor of two traces right of the module, the height by the module on top and a trace under the header. Ground is not routed; it is a copper pour on both sides. There is no copper under the module's antenna, verified with 35 samples on both layers.

Osazená deska shora: modul ESP32-C3-MINI-1, stabilizátor AMS1117, kondenzátory, LED a hřeben J1
Assembled board, top
Deska zespodu se zemní plochou a popisem desky
Bottom: ground pour and label
Měď na horní vrstvě: spoje, plošky a zemní plocha
Top copper
Měď na spodní vrstvě: spoje EN a IO9 a zemní plocha
Bottom copper: EN and IO9 run underneath

What was calculated

These numbers are not estimates. A script computes them directly from the finished board, so they cannot drift from the design.

Current budget

109 mA idle · 344 mA peak

The peak is the module transmitting over Wi-Fi. The module figures are commonly quoted values for now, not from the datasheet.

Power trace width

0.5 mm where 0.134 mm would do

Per IPC-2221 (18 µm copper), 0.134 mm is enough for 344 mA. Half a millimetre is therefore not about heating but about voltage drop and lower inductance.

AMS1117-3.3 regulator

StateLossDie, 25 °C ambient
idle, 109 mA0,19 W36 °C
peak, 344 mA0,58 W61 °C
peak, no copper under the tab0,58 W95 °C

The junction limit is 125 °C. About 1 cm² of copper under the tab is therefore a necessity, not decoration.

Decoupling capacitors

WhereLoopInductance
C3 100nmodule supply5,0 mm2,0 nH
C4 1umodule EN6,1 mm2,4 nH
C2 22uregulator output4,8 mm1,9 nH
C1 10uregulator input5,5 mm2,2 nH

What matters is the area of the current loop, not the distance from the pin. Each capacitor therefore has its own ground via right next to its pad.

Manufacturing is designed for the fab's cheapest standard spec: construction class 5, narrowest trace 0.30 mm, clearance 0.25 mm, drill 0.30 mm. No surcharges.

What is verified and what is not

Verified

  • Schematic: ERC 0 errors, netlist matches the expected nets.
  • Board: DRC against the fab's rules, 0 violations and 0 unconnected pads.
  • Electrical checks by script: currents, trace widths, regulator heating, decoupling, copper under the antenna.
  • Enclosure: checks in the model that the ledge runs under no pin, posts and rib hit no component and the lid does not sit on the header.

Not verified yet

  • The board has not been manufactured and the enclosure has not been printed.
  • Capacitor values, R1 and the EN circuit follow common practice, not the module datasheet.
  • The lid opening assumes a 1x6 Dupont connector; not tried on an actual cable.
  • The 0.2 mm lip clearance will be tuned on the first print.

An enclosure for your board?

Send me your KiCad board. The enclosure is computed from its 3D model and you get STL files for printing plus images for your documentation. Or we start from the schematic.

Send an email

David Petrov · davidpetrov@email.cz